HiPC 2023 Student Research Symposium
30th IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, DATA, & ANALYTICS
Overview
HiPC 2023 will feature the 15th Student Research Symposium (SRS) on High-Performance Computing, Data, and Analytics (HPC) aimed at stimulating and fostering student research, and providing an international forum to highlight student research accomplishments. The symposium will be an integrated part of the main HiPC conference aiming to provide exposure to students to the best practices in HPC in academia and industry.
The symposium will feature student posters and provide students with other enriching experiences, such as workshops, industry exhibits, and demos. In 2023, SRS is enhanced with mentoring sessions, a special keynote speech, expert panel discussion, and lightning talks. The Conference Reception and multiple Student Symposium Poster Exhibit sessions will provide an opportunity for students to interact with HPC researchers and practitioners (and recruiters) from academia and industry.
HiPC will provide limited travel support to one author of selected posters. Awards for Best Poster will be presented at the symposium. An online book containing the resumes of the students participating in the symposium will be compiled and made available to the sponsors of the HiPC 2023 conference to be held between Dec 18th and 21st in Goa, India.
List of Accepted Papers
| Pursuing Degree of Lead Author | Paper Title | Contributors |
| Ph.D. | Towards a Cross-Platform Benchmark Suite for FaaS Workflows | Varad Kulkarni (Indian Institute of Science, Bangalore, India), Nikhil Reddy (Indian Institute of Science, Bangalore, India), Tuhin Khare (Indian Institute of Science, Bangalore, India), Harini Mohan (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Jahnavi Murali (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Mohith A (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Ragul B (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Sanjai Balajee (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Sanjjit S (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Swathika Durairaj (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Vaishnavi S (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Yashasvee V (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Chitra Babu (Sri Sivasubramaniya Nadar College of Engineering, Chennai, India), Abhinandan S Prasad (Indian Institute of Technology, Ropar, India), Yogesh Simmhan (Indian Institute of Science, Bangalore, India) |
| Ph.D. | Fine-grained Communication Profiling of Parallel Applications | Vishal Deka (Indian Institute of Technology Kanpur), Preeti Malakar (Indian Institute of Technology Kanpur) |
| Ph.D. | Towards a Modular Federated Learning Framework on Edge Devices | Roopkatha Banerjee (Indian Institute of Science), Prince Modi (Indian Institute of Science), Harsha Varun Marisetty (Birla Institute of Technology and Science Pilani, Hyderabad), Manik Gupta (Birla Institute of Technology and Science Pilani, Hyderabad), Yogesh Simmhan (Indian Institute of Science) |
| Ph.D. | Hide-n-Seek: Hiding Writes in Buffer for Lifetime Improvement in STT-RAM based LLC | Prabuddha Sinha (Indian Institute of Technology, Ropar), Krishna Prathik BV (Rashtreeya Vidyalaya College of Engineering, Bangalore), Shirshendu Das (Indian Institute of Technology, Hyderabad), Venkata Kalyan Tavva (Indian Institute of Technology, Ropar) |
| Ph.D. | Scaling performance of the asynchronous discontinuous-Galerkin method for compressible Euler equations | Shubham Goswami (Indian Institute of Science, Bengaluru), Dapse Vidyesh (Indian Institute of Science, Bengaluru), Konduri Aditya (Indian Institute of Science, Bengaluru) |
| Ph.D. | Delay-Aware Task Offloading for Mobile Fog Nodes in Smart Cities: A Fuzzy and Q-Learning Approach | Md Asif Thanedar (NIT Warangal), Sanjaya Kumar Panda (NIT Warangal) |
| Ph.D. | Spintronics Main Memory Alternative to DRAM with Reliable Simulations | Kallinatha H D (National Institute of Technology Karnataka Surathkal; SIT,Tumkur), Basavaraj Talawar (National Institute of Technology Karnataka Surathkal) |
| Ph.D. | Efficient Parallel Algorithms for Large Tree Contraction. | AKANKSHA DWIVEDI (Indian Institute of Technology Jodhpur), SAMEER SHARMA (Indian Institute of Technology Jodhpur), DIP SANKAR BANERJEE (Indian Institute of Technology Jodhpur) |
| Ph.D. | An Algorithm to reduce evaluation time of Interpolated Deep Material Network during Hyper parameter tuning | Pavan Bhat Keelanje Srinivas (Fraunhofer Institute for Industrial Mathematics), Matthias Kabel (Fraunhofer Institute for Industrial Mathematics), Matti Schneider (University Of Duisburg Essen) |
| Ph.D. | Enhancing On-Chip Cache Efficiency via Optimized Retention Time in Spintronics Device | ALISHA P B (Cochin University of Science and Technology) |
| Ph.D. | Accelerated Development of Efficient Matrix Multiplication for Heterogeneous Systems. | Bonthu Vyuhita (Indian Institute of Technology, Dharwad), Nikhil D. Hegde (Indian Institute of Technology Dharwad) |
| Ph.D. | Efficient Flag-Based Implementation of Parallel PIC Codes on Shared Memory Architectures | Libin Varghese (Dhirubhai Ambani Institute of Information and Communication Technology), Bhaskar Chaudhury (Dhirubhai Ambani Institute of Information and Communication Technology), Miral Shah (Institute for Plasma Research), Mainak Bandyopadhyay (Institute for Plasma Research, Bhat, Gandhinagar, Gujarat, India; Homi Bhabha National Institute, Anushaktinagar, Mumbai, India) |
| Ph.D. | oneAPI based GPU porting and optimization of a lattice Boltzmann flow solver | Shivakumar Kandre (Indian Institute of Technology Dharwad), Amarpal S. Kapoor (Intel Corporation Bengaluru, India), Nitya Hariharan (Intel Corporation Bengaluru, India), Dhiraj V. Patil (Indian Institute of Technology Dharwad) |
| Ph.D. | CAMOUFLAGE: An Efficient Mechanism to Hide Congestion in NVM LLC | Prathamesh Tanksale (Indian Institute of Technology Ropar), Kousik Kumar Dutta (Indian Institute of Technology Ropar), Shirshendu Das (Indian Institute of Technology Hyderabad), Venkata Kalyan Tavva (Indian Institute of Technology Ropar) |
| Ph.D. | Evaluating Strategies for Federated Graph Learning | Pranjal Naman (Indian Institute of Science), Suved Sanjay Ghanmode (Indian Institute of Science), Yogesh Simmhan (Indian Institute of Science) |
| Ph.D. | Study of time series algorithms & ensemble techniques for real-time weather prediction for a Gamma-ray Experiment | Debangana Sarkar (Homi Bhabha National Institute, Bhabha Atomic Research Centre), Nilesh Chouhan (Bhabha Atomic Research Centre), Kuldeep Yadav (Bhabha Atomic Research Centre, Homi Bhabha National Institute) |
| Ph.D. | Towards Mutable Smart Contracts in A Blockchain | Aishwarya Parab (BITS Pilani, K. K. Birla Goa Campus), Pranay Nandan Varshney (BITS Pilani, K. K. Birla Goa Campus), Nirmal Govindaraj (BITS Pilani, K. K. Birla Goa Campus), Kunal Korgaonkar (BITS Pilani, K. K. Birla Goa Campus), Arnab K. Paul (BITS Pilani, K. K. Birla Goa Campus) |
| Ph.D. | DAIR: Data-Aware Inter-Reference distance based cache replacement for LLC in Systems with Hybrid Memory | Sadhana Rai (National Institute of Technology Karnataka), Basavaraj Talawar (National Institute of Technology Karnataka) |
| Masters | Memory Efficient Sparse Matrix-Matrix Multiplication on GPU | Apurva Dogra (IIT Bhilai), Kishan Tamboli (IIT Bhilai), Vishwesh Jatala (IIT Bhilai) |
| Masters | Accelerating BFS Algorithm on a RISC-V based Many-Core Cluster | M. R. Ashuthosh (PES University), Aakarsh Vinay (PES University), Krishna K. Nagar (Intel Corporation), Madhura Purnaprajna (PES University) |
| Masters | vSlice: Differentiated Provisioning of vGPUs for Inference Platforms | Sameer Ahmad (IIT Bombay), Purushottam Kulkarni (IIT Bombay), Praveen Jayachandran (IBM), Anand Eswaran (IBM) |
| Masters | Visual Analysis of Congestion and Interference in Supercomputers | Akshay Sharma (Indian Institute of Technology Kanpur), Depanshu Sahu (Indian Institute of Technology Kanpur), Preeti Malakar (Indian Institute of Technology Kanpur) |
| Masters | Support for function resource variants with MPS-based GPUs for Kubernetes platforms | Anshul Sanghi (Indian Institute of Technology Bombay), Purushottam Kulkarni (Indian Institute of Technology Bombay) |
| Masters | sflex : Elastic GPU management for slurm workload manager | Sanyasi Sai Sandeep Pothala (IIT Bombay), Purushottam Kulkarni (IIT Bombay) |
| Undergraduate | PeerCompute: Trust Enabled Decentralized Scheduler for Serverless Computing | Satyam Bansal (BITS Pilani, K. K. Birla Goa Campus), Paras Mittal (BITS Pilani, K. K. Birla Goa Campus), Pranay Nandan Varshney (BITS Pilani, K. K. Birla Goa Campus), Arnab K. Paul (BITS Pilani, K. K. Birla Goa Campus) |
| Undergraduate | Modeling Performance of Transformers on FPGA | Madan Y N (Indian Institute of Technology Bombay), Ashwin Krishnan (TCS Research), Manoj Nambiar (TCS Research) |
| Undergraduate | EkatraFL: Enabling Decentralized Cross-Silo Federated Learning | Sarang S (BITS Pilani, K. K. Birla Goa Campus), Yuvraj Singh Bhadauria (BITS Pilani, K. K. Birla Goa Campus), Druva Dhakshinamoorthy (BITS Pilani, K. K. Birla Goa Campus), Arihant Bansal (BITS Pilani, K. K. Birla Goa Campus), Pinki Yadav (BITS Pilani, K. K. Birla Goa Campus), Aditya Shiva Sharma (BITS Pilani, K. K. Birla Goa Campus), Arnab K. Paul (BITS Pilani, K. K. Birla Goa Campus) |
| Undergraduate | Performance Comparison and Classification of Concurrent Algorithms on CPU and GPU | Geetham Talluri (Indian Institute of Technology Dharwad, Defence Research Development Laboratories), Eshwar Uppu (Indian Institute of Technology Hyderabad, Defence Research Development Laboratories), Jatin Lather (Indian Institute of Technology Dharwad, Defence Research Development Laboratories) |
| High School | AI-based Soil Fertility Quality Estimation from Remote Sensing Data | Ayush Talukder (Montgomery Blair High School (STEM Magnet Program), Univ of Southern California (Intern)), Cauligi Raghavendra (University of Southern California), Elizabeth Glenn (Montgomery Blair High School) |
Call for Papers
Papers are solicited in all areas of high-performance computing, data, and analytics, including but not limited to the topics mentioned in the HiPC Call for Papers.
Important Dates*
Submission Opens: Aug 22, 2023
Submission Deadline: Sep 30, 2023 Oct 9, 2023
Accept/Reject Decision Notification: Nov 6, 2023
Camera-ready Deadline for the Abstract of Accepted Posters: Nov 13, 2023
Symposium: Dec 18-21, 2023
*All deadlines are in AoE – Anywhere on Earth
Eligibility
Submissions should have at least one author who is a student during any part of the calendar year 2023. Submissions may have multiple student or non-student co-authors. Submissions must mark student authors and with an asterisk (*). Student authors should also specify the degree they are pursuing.
Submission Instructions
In order to be considered for a poster at the Student Research Symposium, authors must submit papers not exceeding two (2) single-spaced double-column pages (including references) using 10-point size font on 8.5×11 inch pages, with 1” margins on all sides (IEEE conference style). The IEEE conference style templates for MS Word and LaTeX provided by IEEE eXpress Conference Publishing are available for download. See the latest versions here.
Papers are to be submitted online in PDF format through https://ssl.linklings.net/conferences/HiPC/.
During submission, it needs to be marked whether the lead author is an undergraduate (B.E./B.Tech.), a postgraduate (M.E./M.Tech.) or a Ph.D. student.
A signed letter from the academic advisor needs to be submitted which states that “the submitted work is original and the work is done by the student”.
The poster authors are encouraged to follow the following format for the two page submission.
Introduction (0.5 page): Answer the following in separate paragraphs.
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- Motivation. Clearly state the objective of the paper and motivate the specific problem your work is solving.
- Limitation of the state-of-art approaches. Briefly review the most relevant and most recent prior works. Clearly articulate the limitations of prior works and how your approach breaks away from those limitations.
- Key insights and contributions. Briefly articulate the major insights that enable your approach. Clearly specify the novelty of these insights and how they advance state-of-the-art.
- Limitations of the proposed approach. Clearly articulate the major limitations of the proposed approach and identify avenues of future work.
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- Design (0.5 page): Explain the overall design of your work with a brief explanation of the major components. It is better to include a small figure.
- Evaluation (0.5 page): Explain the testbed and include the major experimental results with graphs (if applicable).
- Conclusion and Future Work (0.3 page): Derive major conclusions of your work and specify future directions of the research.
- References (0.2 page): 4-5 major references for the work which are cited in the paper.
Some sample 2-page posters are provided below which were accepted in SC 2022.
- https://sc22.supercomputing.org/proceedings/tech_poster/poster_files/rpost142s3-file3.pdf
- https://sc22.supercomputing.org/proceedings/tech_poster/poster_files/rpost183s3-file3.pdf
- https://sc22.supercomputing.org/proceedings/tech_poster/poster_files/rpost193s3-file3.pdf
One page abstracts of the selected posters will be published in the HiPC Workshop proceedings in IEEE Xplore. This will provide students the flexibility to publish an extended version of their paper at other venues, after benefiting from reviewer feedback from the symposium. Papers submitted to the symposium are expected to be reviewed by at least three independent reviewers. Papers will be judged on technical merit, quality, relevance to the symposium, and related parameters. Plagiarism, in any form, especially verbatim reproduction from other published works, is prohibited. Papers that are plagiarized will be rejected, and the corresponding department and institution will be notified.
As per IEEE guidelines, the use of artificial intelligence (AI)–generated text in an article needs to be disclosed in the acknowledgements section of any submitted paper. The sections of the paper that use AI-generated text should have a citation to the AI system used to generate the text. For more information, please click here.
Facilities for displaying posters will be made available, and the exact specifications of the poster size will be provided later. At least one student author of each paper that is accepted must register and attend the conference to present their work. Papers with no-shows will be retroactively rejected.
Travel Support
HiPC will provide a limited travel scholarship to at least one student author of each accepted submission from an Indian university. There may be a small number of travel scholarships for international student authors. This scholarship will cover partial expenses for attending the conference. To get reimbursement of travel support, SRS organizers expect the selected students to attend the entire conference along with the SRS-specific activities. Further details on this scholarship and the application process will be provided later.
Mentoring Session
Mentoring will be organized to the students selected for SRS, where the students will get an opportunity to meet senior researchers attending the HiPC conference. These mentoring sessions include a panel of experts providing their experiences in research and a lunch where a mentor will be matched with students. More mentoring opportunities are being planned for SRS students to get guidance to the world of R&D in high-performance computing.
Symposium Co-chairs
Arnab K. Paul, Birla Institute of Technology and Science Pilani, Goa Campus, India
Suren Byna, Ohio State University, USA
Program Committee
Amit Majumdar, San Diego Supercomputer Center, USA
Dip Sankar Banerjee, Indian Institute of Technology Jodhpur, India
Jean Luca Bez, Lawrence Berkeley National Laboratory, USA
Konduri Aditya, Indian Institute of Science, India
M. Mustafa Rafique, Rochester Institute of Technology, USA
Nikhil Hegde, Indian Institute of Technology Dharwad, India
Nitin Auluck, Indian Institute of Technology Ropar, India
Preeti Malakar, Indian Institute of Technology Kanpur, India
Sameer Shende, University of Oregon, USA
Sanket Tavarageri, Microsoft, India
Sarah, Neuwirth, Johannes Gutenberg University Mainz, Germany
Suresh Purini, International Institute of Information Technology Hyderabad, India
Tanu Malik, DePaul University, USA
Vishwesh Jatala, Indian Institute of Technology Bhilai, India
Vivek Kumar, Indraprastha Institute of Information Technology, Delhi, India
Contact
Contact <student_symposium at hipc dot org> for more details.